A typical example of a heterogeneous structure is the Si(1-x)Ge(x) structure which includes a relaxed Si(1-x)Ge(x) buffer layer that is epitaxially grown on a Si substrate. Such a heterogeneous structure is described in the paper entitled “Planarization of SiGe virtual substrate by CMP and its application to strained Si modulation-doped structures”, by K. Sawano et al, published in Journal of Crystal Growth, V251, pp 693-696 (2003). As shown in FIG. 1 herein, such a hetero-structure 100 comprises a strained relaxed Si(1-x)Ge(x) buffer layer 105, which consists of a compositionally step-graded Si(1-x)Ge(x) (x=0−0.3) layer 102 (300 nm) and uniform Si(0.7)Ge(0.3) layer 103 (1 μm), that is grown on a p-type Si substrate 101.
As a result of the lattice constant mismatch between the substrate and subsequent layers, a relaxation crosshatch pattern 104 is created at the top surface. FIG. 2 shows an image of the surface morphology of a strain-relaxed SiGe buffer layer performed by an atomic force microscope (AFM). The crosshatch exhibits an initial roughness of 3.2 nm, with a peak-valley of 21.2 nm, for a scan area of 40*40 μm. Thus, surface variations associated with this crosshatch pattern must be minimized by appropriate polishing prior to further epitaxy, such as, for example, before growing the Si(0.7)Ge(0.3) buffer layer (100 nm), Si channel layer (15 nm) and Si(0.7)Ge(0.3) spacer layer (20 nm).
After this donor wafer is fabricated, a transfer process is performed in order to detach and transfer a part of the upper layer(s) from this “engineered” substrate to a handle substrate. An example of such a transfer process is the SMART-CUT® technology which is described notably in the article by A. J. Auberton-Hervé et al entitled “Why can Smart Cut change the future of microelectronics?”, Int. Journal of High Speed Electronics and Systems, Vol. 10, no. 1, 2000, pp 131-146. This approach implements an ion implantation step to create a weakened or cleavage zone in the donor wafer, and bonding the implanted face of that wafer to a handle substrate, followed by mechanical detachment or cleaving of a useful layer from the donor wafer. The mechanical detachment results in a damaged zone on the final top surface which must be polished in order to obtain the required smoothness for the useful layer.
During the recycling of silicon or Si(1-x)Ge(x) donor substrates after conducting such a transfer process, polishing processes are implemented to decrease the surface roughness and eliminate the damaged zone of the donor wafer that is to be recycled. In this case, the polishing is performed in one or several steps (including a planarization step followed by a finishing step).
These situations are all characterized by a disturbed zone (crosshatch pattern in the first case, or of after-detachment residues in the other cases), of a given thickness, existing on a substrate, which has to be eliminated or smoothened. Techniques for eliminating crosshatch patterns and reducing the surface roughness of Si(1-x)Ge(x) substrates have been previously reported by K. Sawano et al. in Journal of Crystal Growth, as mentioned above, and in Material and Science Engineering, in a paper entitled “Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing” (B89, pp 406-409, 2002). A roughness of root mean square (RMS) values less than 1 nm (around 0.4 nm over 10*10 μm2 surfaces) after polishing the Si(1-x)Ge(x) substrate is reported. However, the polishing rates achieved for this kind of process are relatively slow, namely, a maximum polishing rate of only 13 Å/sec is obtained.
Moreover, the finishing process of a silicon layer of a Si-on-insulator (SOI) material by chemical-mechanical polishing, such as disclosed in U.S. Pat. No. 6,988,936, as well as that for the recycling of a silicon peeled wafer such as disclosed in the Japanese patent publication JP-A-11 297583, are not appropriate to materials such as SiGe material because the polishing rate is too slow. In particular, the Si(1-x)Ge(x) polishing rate is lower by a factor of 5 versus that for polishing Si. Accordingly, improved polishing processes for such materials is needed, and these are now provided by the present invention.